HD64F3048F16 Datasheet, PDF (246/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 8 DMA Controller
Bit 6—Reserved: Although reserved, this bit can be written and read.
Bit 5—Destination Address Increment/Decrement (DAID) and
Bit 4—Destination Address Increment/Decrement Enable (DAIDE): These bits select whether
the destination address register (MARB) is incremented, decremented, or held fixed during the
data transfer.
Bit 5: DAID
0
1
Bit 4: DAIDE
0
1
0
1
Description
MARB is held fixed
(Initial value)
MARB is incremented after each data transfer
• If DTSZ = 0, MARB is incremented by 1 after each
data transfer
• If DTSZ = 1, MARB is incremented by 2 after each
data transfer
MARB is held fixed
MARB is decremented after each data transfer
• If DTSZ = 0, MARB is decremented by 1 after each
data transfer
• If DTSZ = 1, MARB is decremented by 2 after each
data transfer
Bit 3—Transfer Mode Select (TMS): Selects whether the source or destination is the block area
in block transfer mode.
Bit 3: TMS
0
1
Description
Destination is the block area in block transfer mode
Source is the block area in block transfer mode
(Initial value)
Rev. 3.00 Sep 27, 2006 page 218 of 872
REJ09B0325-0300