HD64F3048F16 Datasheet, PDF (412/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 10 16-Bit Integrated Timer Unit (ITU)
TCNT4
T
T−1
H'0000
H'FFFF
TCNT3
Illegal changes
Figure 10.41 Changing a General Register Setting by Buffer Transfer (Caution 2)
 General register settings outside the counting range (H'0000 to GRA3)
Waveforms with a duty cycle of 0% or 100% can be output by setting a general register to
a value outside the counting range. When a buffer register is set to a value outside the
counting range, then later restored to a value within the counting range, the counting
direction (up or down) must be the same both times. See figure 10.42.
GRA3
GR
H'0000
Output pin
Output pin
BR
0% duty cycle
100% duty cycle
GR
Write during down-counting
Write during up-counting
Figure 10.42 Changing a General Register Setting by Buffer Transfer (Example 2)
Settings can be made in this way by detecting GRA3 compare match or TCNT4 underflow
before writing to the buffer register. They can also be made by using GRA3 compare match
to activate the DMAC.
Rev. 3.00 Sep 27, 2006 page 384 of 872
REJ09B0325-0300