HD64F3048F16 Datasheet, PDF (56/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 1 Overview
1.5 Setting Oscillation Settling Wait Time
When software standby mode is used, after exiting software standby mode a wait period must be
provided to allow the clock to stabilize. Select the length of time for which the CPU and
peripheral functions are to wait by setting bits STS2 to STS0 in the system control register
(SYSCR) and bits DIV1 and DIV0 in the division ratio control register (DIVCR) according to the
operating frequency of the chip.
For the H8/3048B Group, ensure that the oscillation settling wait time is at least 0.1 ms when
operating on an external clock.
For setting details, see section 20.4.3, Selection of Waiting Time for Exit from Software Standby
Mode.
1.6 Notes on Crystal Resonator Connection
The H8/3048B Group support an operating frequency of up to 25 MHz. If a crystal resonator with
a frequency higher than 20 MHz is connected, attention must be paid to circuit constants such as
external load capacitance values. For details see section 19.2.1, Connecting a Crystal Resonator.
Rev. 3.00 Sep 27, 2006 page 28 of 872
REJ09B0325-0300