HD64F3048F16 Datasheet, PDF (45/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Type
Bus control
Refresh
controller
Section 1 Overview
Symbol
CS₇ to CS₀
AS
RD
HWR
LWR
WAIT
RFSH
CS₃
RD
HWR
LWR
Pin No.
I/O
8, 97 to 99, Output
88 to 91
69
Output
70
Output
71
Output
72
Output
58
Input
87
Output
88
Output
70
Output
71
Output
72
Output
Name and Function
Chip select: Select signals for areas 7 to 0
Address strobe: Goes low to indicate valid
address output on the address bus
Read: Goes low to indicate reading from
the external address space
High write: Goes low to indicate writing to
the external address space; indicates valid
data on the upper data bus (D to D ).
15
8
Low write: Goes low to indicate writing to
the external address space; indicates valid
data on the lower data bus (D₇ to D₀).
Wait: Requests insertion of wait states in
bus cycles during access to the external
address space
Refresh: Indicates a refresh cycle
Row address strobe RAS: Row address
strobe signal for DRAM connected to area 3
Column address strobe CAS: Column
address strobe signal for DRAM connected
to area 3; used with 2WE DRAM.
Write enable WE: Write enable signal for
DRAM connected to area 3; used with
2CAS DRAM.
Upper write UW: Write enable signal for
DRAM connected to area 3; used with 2WE
DRAM.
Upper column address strobe UCAS:
Column address strobe signal for DRAM
connected to area 3; used with 2CAS
DRAM.
Lower write LW: Write enable signal for
DRAM connected to area 3; used with 2WE
DRAM.
Lower column address strobe LCAS:
Column address strobe signal for DRAM
connected to area 3; used with 2CAS
DRAM.
Rev. 3.00 Sep 27, 2006 page 17 of 872
REJ09B0325-0300