HD64F3048F16 Datasheet, PDF (802/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Appendix B Internal I/O Register
RAMCR—RAM Control Register
H'47
Flash memory
Bit
7
6
5
4
3
2
1
0



 RAMS RAM2 RAM1 
Modes ^{Initial value}
1
1
1
1
0
0
0
0
1 to 4 Read/Write




R
R
R

Modes ^{Initial value}
1
1
1
1
0
0
0
0
5 to 7 _Read/Write




R/W
R/W
R/W
R/W
Reserved bits
RAM select, RAM2, RAM1
Bit 3 Bit 2 Bit 1
RAMS RAM2 RAM1
RAM Area
0
0/1 0/1 H'FFF000 to H'FFF3FF
1
0
0 H'000000 to H'0003FF
1 H'000400 to H'0007FF
1
0 H'000800 to H'000BFF
1 H'000C00 to H'000FFF
RAM Emulation Status
No emulation
Mapping RAM
Note: Bits 7 to 4 are reserved and cannot be modified.
If data is written to these bits, normal operation is not guaranteed.
Bit 0 is a reserved bit but is readable/writable.
H8/3048F-ONE
Include this register
H8/3048B mask ROM version Not include this register
H8/3048F
H8/3048ZTAT
H8/3048 mask ROM version
H8/3047 mask ROM version
H8/3045 mask ROM version
H8/3044 mask ROM version
Rev. 3.00 Sep 27, 2006 page 774 of 872
REJ09B0325-0300