HD64F3048F16 Datasheet, PDF (617/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 18 ROM (H8/3048F-ONE: Single Power Supply, H8/3048B Mask ROM Version)
18.5.3 Erase Block Register (EBR)
EBR is an 8-bit register that designates the flash memory block for erasure. EBR is initialized to
H'00 by a reset, in hardware standby mode or software standby mode, when a high level is not
input to the FWE pin, or when the SWE bit in FLMCR1 is 0 when a high level is applied to the
FWE pin. When a bit is set in EBR, the corresponding block can be erased. Other blocks are erase-
protected. The blocks are erased block by block. Therefore, set only one bit in EBR; do not set bits
in EBR to erase two or more blocks at the same time.
Each bit in EBR cannot be set until the SWE bit in FLMCR1 is set. The flash memory block
configuration is shown in table 18.4. To erase all the blocks, erase each block sequentially.
Bit
7
6
5
4
3
2
1
0
EB7
EB6 EB5
EB4
EB3
EB2
EB1
EB0
Modes ^{Initial value}
0
0
0
0
0
0
0
0
1 to 4 Read/Write
R
R
R
R
R
R
R
R
Modes ^{Initial value}
0
0
0
0
0
0
0
0
5 to 7 _{Read/Write R/W}
R/W
R/W
R/W R/W
R/W
R/W R/W
Bits 7 to 0—Block 7 to Block 0 (EB7 to EB0): Setting one of these bits specifies the
corresponding block (EB7 to EB0) for erasure.
Bits 7–0:
EB7–EB0
Description
0
Corresponding block (EB7 to EB0) not selected
1
Corresponding block (EB7 to EB0) selected
Note: When not performing an erase, clear EBR to H'00.
(Initial value)
Rev. 3.00 Sep 27, 2006 page 589 of 872
REJ09B0325-0300