HD64F3048F16 Datasheet, PDF (671/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 20 Power-Down State
20.2.2 Module Standby Control Register (MSTCR)
MSTCR is an 8-bit readable/writable register that controls output of the system clock (φ). It also
controls the module standby function, which places individual on-chip supporting modules in the
standby state. Module standby can be designated for the ITU, SCI0, SCI1, DMAC, refresh
controller, and A/D converter modules.
Bit
Initial value
Read/Write
7
PSTOP
0
R/W
6
5
4
3
2
1
0
 MSTOP5 MSTOP4 MSTOP3 MSTOP2 MSTOP1 MSTOP0
1
0
0
0
0
0
0

R/W
R/W R/W
R/W
R/W R/W
Reserved bit
φ clock stop
Enables or disables
output of the system clock
Module standby 5 to 0
These bits select modules
to be placed in standby
MSTCR is initialized to H'40 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—φ Clock Stop (PSTOP): Enables or disables output of the system clock (φ).
Bit 1: PSTOP
0
1
Description
System clock output is enabled
System clock output is disabled
(Initial value)
Bit 6—Reserved: Read-only bit, always read as 1.
Bit 5—Module Standby 5 (MSTOP5): Selects whether to place the ITU in standby.
Bit 5: MSTOP5
0
1
Description
ITU operates normally
ITU is in standby state
(Initial value)
Rev. 3.00 Sep 27, 2006 page 643 of 872
REJ09B0325-0300