HD64F3048F16 Datasheet, PDF (561/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 14 Smart Card Interface
(1) Data write
TDR
Data 1
TSR
(shift register)
(2) Transfer from
TDR to TSR
(3) Serial data output
Data 1
Data 1
Data 1
; Data remains in TDR
Data 1 _{I/O signal line output}
In case of normal transmission: TEND flag is set
In case of transmit error:
ERS flag is set
Steps (2) and (3) above are repeated until the TEND flag is set
Note: When the ERS flag is set, it should be cleared until transfer of the last bit (D7 in LSB-first
transmission, D0 in MSB-first transmission) of the next transfer data to be transmitted has
been completed.
Figure 14.5 Relation Between Transmit Operation and Internal Registers
I/O data
Ds Da Db Dc Dd De Df Dg Dh Dp
DE
TXI
(TEND interrupt)
12.5 etu
Guard
time
When GM = 0
11.0 etu
When GM = 1
Figure 14.6 TEND Flag Occurrence Timing
Rev. 3.00 Sep 27, 2006 page 533 of 872
REJ09B0325-0300