HD64F3048F16 Datasheet, PDF (635/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 18 ROM (H8/3048F-ONE: Single Power Supply, H8/3048B Mask ROM Version)
18.7.3 Erase Mode
To erase an individual flash memory block, follow the flowchart for erasing one block (single-
block erase) shown in figure 18.14.
The wait times after bits are set or cleared in the flash memory control register 1 (FLMCR1) and
the maximum number of erase operations (N) are shown in table 21.11 in section 21.1.6, Flash
Memory Characteristics.
To erase flash memory contents, make a 1-bit setting for the flash memory area to be erased in
erase block register (EBR1) at least (t_sswe) µs after setting the SWE bit to 1 in FLMCR1. Next, the
watchdog timer (WDT) is set to prevent overerasing due to program runaway, etc. Set a value
greater than (t_se) ms + (t_sesu + t_ce + t_cesu) µs as the WDT overflow period. Preparation for entering
erase mode (erase setup) is performed next by setting the ESU bit in FLMCR1. The operating
mode is then switched to erase mode by setting the E bit in FLMCR1 after the elapse of at least
(t_sesu) µs. The time during which the E bit is set is the flash memory erase time. Ensure that the
erase time does not exceed (t_se) ms.
Note: With flash memory erasing, preprogramming (setting all memory data in the memory to
be erased to all 0) is not necessary before starting the erase procedure.
18.7.4 Erase-Verify Mode
In erase-verify mode, data is read after memory has been erased to check whether it has been
correctly erased.
After the elapse of the fixed erase time, clear the E bit in FLMCR1, then wait for at least (t_ce) µs
before clearing the ESU bit to exit erase mode. After exiting erase mode, the watchdog timer
setting is also cleared. The operating mode is then switched to erase-verify mode by setting the EV
bit in FLMCR1. Before reading in erase-verify mode, a dummy write of H'FF data should be made
to the addresses to be read. The dummy write should be executed after the elapse of (t_sev) µs or
more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at
the latched address is read. Wait at least (t_sevr) µs after the dummy write before performing this read
operation. If the read data has been erased (all 1), a dummy write is performed to the next address,
and erase-verify is performed. If the read data is unerased, set erase mode again, and repeat the
erase/erase-verify sequence as before. The maximum value for repetition of the erase/erase-verify
sequence is indicated by the maximum erase count (N). When verification is completed, exit
erase-verify mode, and wait for at least (t_cev) µs. If erasure has been completed on all the erase
blocks, clear bit SWE1 in FLMCR1, and leave a wait time of at least (t_cswe) µs.
Rev. 3.00 Sep 27, 2006 page 607 of 872
REJ09B0325-0300