HD64F3048F16 Datasheet, PDF (285/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 8 DMA Controller
8.6.8 Bus Cycle when Transfer Is Aborted
When a transfer is aborted by clearing the DTE bit or suspended by an NMI that clears the DTME
bit, if this halts a channel for which the DMAC has a transfer request pending internally, a dead
cycle may occur. This dead cycle does not update the halted channel’s address register or counter
value. Figure 8.27 shows an example in which an auto-requested transfer in cycle-steal mode on
channel 0 is aborted by clearing the DTE bit in channel 0.
CPU cycle
DMAC cycle
CPU cycle
DMAC
cycle
CPU cycle
T₁ T₂ T_d T₁ T₂ T₁ T₂ T₁ T₂ T₃ T_d T_d T₁ T₂
φ
Address bus
RD
HWR, LWR
DTE bit is
cleared
Figure 8.27 Bus Timing at Abort of DMA Transfer in Cycle-Steal Mode
Rev. 3.00 Sep 27, 2006 page 257 of 872
REJ09B0325-0300