HD64F3048F16 Datasheet, PDF (489/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 13 Serial Communication Interface
13.2.5 Serial Mode Register (SMR)
SMR is an 8-bit register that specifies the SCI serial communication format and selects the clock
source for the baud rate generator.
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
C/A
CHR
PE
O/E STOP MP CKS1 CKS0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W R/W
R/W
R/W
R/W
Clock select 1/0
These bits select the
baud rate generator’s
clock source
Multiprocessor mode
Selects the multiprocessor
function
Stop bit length
Selects the stop bit length
Parity mode
Selects even or odd parity
Parity enable
Selects whether a parity bit is added
Character length
Selects character length in asynchronous mode
Communication mode
Selects asynchronous or synchronous mode
The CPU can always read and write SMR. SMR is initialized to H'00 by a reset and in standby
mode.
Bit 7—Communication Mode (C/A): Selects whether the SCI operates in asynchronous or
synchronous mode.
Bit 7: C/A
0
1
Description
Asynchronous mode
Synchronous mode
(Initial value)
Rev. 3.00 Sep 27, 2006 page 461 of 872
REJ09B0325-0300