HD64F3048F16 Datasheet, PDF (435/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 10 16-Bit Integrated Timer Unit (ITU)
Contention between General Register Write and Input Capture
If an input capture signal occurs in the T₃ state of a general register write cycle, input capture takes
priority and the write to the general register is not performed. See figure 10.68.
General register write cycle
T₁
T₂
T₃
φ
Address bus
GR address
Internal write signal
Input capture signal
TCNT
M
GR
M
Figure 10.68 Contention between General Register Write and Input Capture
Note on Waveform Period Setting
When a counter is cleared by compare match, the counter is cleared in the last state at which the
TCNT value matches the general register value, at the time when this value would normally be
updated to the next count. The actual counter frequency is therefore given by the following
formula:
f= ^φ
(N + 1)
(f: counter frequency. φ: system clock frequency. N: value set in general register.)
Rev. 3.00 Sep 27, 2006 page 407 of 872
REJ09B0325-0300