HD64F3048F16 Datasheet, PDF (863/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

IER—IRQ Enable Register
Appendix B Internal I/O Register
H'F5 Interrupt controller
Bit
7
6
5
4
3
2
1
0

 IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W R/W
IRQ₅ to IRQ₀ enable
0 IRQ ₅ to IRQ₀ interrupts are disabled
1 IRQ ₅ to IRQ₀ interrupts are enabled
ISR—IRQ Status Register
H'F6 Interrupt controller
Bit
7

Initial value
0
Read/Write

6
5
4
3
2
1
0
 IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F
0
0
0
0
0
0
0
 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
IRQ₅ to IRQ ₀ flags
Bits 5 to 0
IRQ5F to IRQ0F
0
Setting and Clearing Conditions
[Clearing conditions]
Read IRQnF when IRQnF = 1, then write 0 in IRQnF.
IRQnSC = 0, IRQn input is high, and interrupt exception
handling is carried out.
IRQnSC = 1 and IRQn interrupt exception handling is
carried out.
1
[Setting conditions]
IRQnSC = 0 and IRQn input is low.
IRQnSC = 1 and a falling edge is generated in the IRQn input.
(n = 5 to 0)
Note: * Only 0 can be written, to clear the flag.
Rev. 3.00 Sep 27, 2006 page 835 of 872
REJ09B0325-0300