HD64F3048F16 Datasheet, PDF (214/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 7 Refresh Controller
Pseudo-Static RAM Control Signals
Figure 7.15 shows the control signals for pseudo-static RAM read, write, and refresh cycles.
φ
Address
bus
CS ₃
RD
HWR
LWR
RFSH
AS
Read cycle
Write cycle *
Refresh cycle
Area 3 top address
Note: * 16-bit access
Figure 7.15 Pseudo-Static RAM Control Signal Output Timing
Refresh Cycle Priority Order
When there are simultaneous bus requests, the priority order is:
(High) External bus master > refresh controller > DMA controller > CPU (Low)
For details see section 6.3.7, Bus Arbiter Operation.
Wait State Insertion
When bit AST3 is set to 1 in ASTCR, the wait state controller (WSC) can insert wait states into
bus cycles and refresh cycles. For details see section 6.3.5, Wait Modes.
Rev. 3.00 Sep 27, 2006 page 186 of 872
REJ09B0325-0300