HD64F3048F16 Datasheet, PDF (206/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 7 Refresh Controller
Operation in Power-Down State
The refresh controller operates in sleep mode. It does not operate in hardware standby mode. In
software standby mode RTCNT is initialized, but RFSHCR, RTMCSR bits 5 to 3, and RTCOR
retain their settings prior to the transition to software standby mode.
Example 1: Connection to 2WE 1-Mbit DRAM (1-Mbyte Mode)
Figure 7.7 shows typical interconnections to a 2WE 1-Mbit DRAM, and the corresponding
address map. Figure 7.8 shows a setup procedure to be followed by a program for this example.
After power-up the DRAM must be refreshed to initialize its internal state. Initialization takes a
certain length of time, which can be measured by using an interrupt from another timer module, or
by counting the number of times RTMCSR bit 7 (CMF) is set. Note that no refresh cycle is
executed for the first refresh request after exit from the reset state or standby mode (the first time
the CMF flag is set; see figure 7.3). When using this example, check the DRAM device
characteristics carefully and use a procedure that fits them.
H8/3048B Group
A₈
A₇
A₆
A₅
A₄
A₃
A₂
A₁
2WE 1-Mbit DRAM with
× 16-bit organization
A₇
A₆
A₅
A₄
A₃
A₂
A₁
A₀
CS ₃
RD
HWR
LWR
D₁₅ to D ₀
RAS
CAS
UW
LW
OE
I/O₁₅ to I/O ₀
a. Interconnections (example)
H'60000
H'7FFFF
DRAM area
Area 3 (1-Mbyte mode)
b. Address map
Figure 7.7 Interconnections and Address Map for 2WE 1-Mbit DRAM (Example)
Rev. 3.00 Sep 27, 2006 page 178 of 872
REJ09B0325-0300