 English |
|
|
|
|
|
|
|
| HD64F3048F16 Datasheet, PDF (725/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents | |||
| |||
| ◁ |
Section 21 Electrical Characteristics
Ï
A9 to A1
AS
CS 3 (RAS)
HWR (UCAS),
LWR (LCAS)
RD (WE)
RFSH
T1
T2
tASD
tCSR
tASD
tRAD2
tRAD2
tCSR
T3
tSD
tRAD3
tSD
tRAD3
Figure 21.14 DRAM Bus Timing (Refresh Cycle): Three-State Access
â 2CAS Mode â
Ï
CS 3 (RAS)
tCSR
HWR (UCAS),
tCSR
LWR (LCAS)
RFSH
Figure 21.15 DRAM Bus Timing (Self-Refresh Mode)
â 2CAS Mode â
Rev. 3.00 Sep 27, 2006 page 697 of 872
REJ09B0325-0300
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese