HD64F3048F16 Datasheet, PDF (191/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

7.2 Register Descriptions
Section 7 Refresh Controller
7.2.1 Refresh Control Register (RFSHCR)
RFSHCR is an 8-bit readable/writable register that selects the operating mode of the refresh
controller.
Bit
7
6
5
4
3
2
1
0
SRFMD PSRAME DRAME CAS/WE M9/M8 RFSHE  RCYCE
Initial value
0
0
0
0
0
0
1
0
Read/Write
R/W R/W R/W R/W R/W R/W

R/W
Refresh cycle
enable
Enables or
disables
insertion of
refresh cycles
Reserved bit
Refresh pin enable
Enables refresh signal output
from the refresh pin
Address multiplex mode select
Selects the number of column address bits
Strobe mode select
Selects 2CAS or 2WE strobing of DRAM
PSRAM enable and DRAM enable
These bits enable or disable connection of pseudo-static RAM and DRAM
Self-refresh mode
Selects self-refresh mode
RFSHCR is initialized to H'02 by a reset and in hardware standby mode.
Rev. 3.00 Sep 27, 2006 page 163 of 872
REJ09B0325-0300