HD64F3048F16 Datasheet, PDF (680/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 20 Power-Down State
20.7 System Clock Output Disabling Function
Output of the system clock (φ) can be controlled by the PSTOP bit in MSTCR. When the PSTOP
bit is set to 1, output of the system clock halts and the φ pin is placed in the high-impedance state.
Figure 20.3 shows the timing of the stopping and starting of system clock output. When the
PSTOP bit is cleared to 0, output of the system clock is enabled. Table 20.4 indicates the state of
the φ pin in various operating states.
MSTCR write cycle
(PSTOP = 1)
MSTCR write cycle
(PSTOP = 0)
T1 T2 T3
T1 T2 T3
φ pin
High-impedance
Figure 20.3 Starting and Stopping of System Clock Output
Table 20.4 φ Pin State in Various Operating States
Operating State
Hardware standby
Software standby
Sleep mode
Normal operation
PSTOP = 0
High-impedance
Always high
System clock output
System clock output
PSTOP = 1
High-impedance
High-impedance
High-impedance
High-impedance
Rev. 3.00 Sep 27, 2006 page 652 of 872
REJ09B0325-0300