HD64F3048F16 Datasheet, PDF (665/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 19 Clock Pulse Generator
19.5.1 Register Configuration
Table 19.5 summarizes the frequency division register.
Table 19.5 Frequency Division Register
Address^*
Name
Abbreviation
H'FF5D
Division control register
DIVCR
Note: * The lower 16 bits of the address are shown.
R/W
Initial Value
R/W
H'FC
19.5.2 Division Control Register (DIVCR)
DIVCR is an 8-bit readable/writable register that selects the division ratio of the frequency
divider.
Bit
7

Initial value
1
Read/Write

6
5
4
3




1
1
1
1




Reserved bits
2
1
0

DIV1 DIV0
1
0
0

R/W R/W
Divide bits 1 and 0
These bits select the
frequency division ratio
DIVCR is initialized to H'FC by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 2—Reserved: Read-only bits, always read as 1.
Bits 1 and 0—Divide (DIV1 and DIV0): These bits select the frequency division ratio, as
follows.
Bit 1: DIV1
0
1
Bit 0: DIV0
0
1
0
1
Frequency Division Ratio
1/1
1/2
1/4
1/8
(Initial value)
Rev. 3.00 Sep 27, 2006 page 637 of 872
REJ09B0325-0300