HD64F3048F16 Datasheet, PDF (179/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Bus Controller
6.3.6 Interconnections with Memory (Example)
For each area, the bus controller can select two- or three-state access and an 8- or 16-bit data bus
width. In three-state-access areas, wait states can be inserted in a variety of modes, simplifying the
connection of both high-speed and low-speed devices.
Figure 6.18 shows an example of interconnections between the H8/3048B Group and memory.
Figure 6.17 shows a memory map for this example.
A 256-kword × 16-bit EPROM is connected to area 0. This device is accessed in three states via a
16-bit bus.
Two 32-kword × 8-bit SRAM devices (SRAM1 and SRAM2) are connected to area 1. These
devices are accessed in two states via a 16-bit bus.
One 32-kword × 8-bit SRAM (SRAM3) is connected to area 2. This device is accessed via an 8-bit
bus, using three-state access with an additional wait state inserted in pin auto-wait mode.
H'000000
H'07FFFF
H'1FFFFF
H'200000
H'20FFFF
H'210000
H'3FFFFF
H'400000
H'407FFF
H'5FFFFF
EPROM
Not used
SRAM 1, 2
Not used
SRAM 3
Not used
Area 0
16-bit, three-state-access area
Area 1
16-bit, two-state-access area
Area 2
8-bit, three-state-access area
(one auto-wait state)
H'FFFFFF
On-chip RAM
Internal I/O registers
Figure 6.17 Memory Map (Example)
Rev. 3.00 Sep 27, 2006 page 151 of 872
REJ09B0325-0300