HD64F3048F16 Datasheet, PDF (151/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Bus Controller
Section 6 Bus Controller
6.1 Overview
The H8/3048B Group has an on-chip bus controller that divides the address space into eight areas
and can assign different bus specifications to each. This enables different types of memory to be
connected easily.
A bus arbitration function of the bus controller controls the operation of the DMA controller
(DMAC) and refresh controller. The bus controller can also release the bus to an external device.
6.1.1 Features
Features of the bus controller are listed below.
• Independent settings for address areas 7 to 0
 128-kbyte areas in 1-Mbyte modes; 2-Mbyte areas in 16-Mbyte modes.
 Chip select signals (CS₇ to CS₀) can be output for areas 7 to 0.
 Areas can be designated for 8-bit or 16-bit access.
 Areas can be designated for two-state or three-state access.
• Four wait modes
 Programmable wait mode, pin auto-wait mode, and pin wait modes 0 and 1 can be selected.
 Zero to three wait states can be inserted automatically.
• Bus arbitration function
 A built-in bus arbiter arbitrates the bus right to the CPU, DMAC, refresh controller, or an
external bus master.
Rev. 3.00 Sep 27, 2006 page 123 of 872
REJ09B0325-0300