HD64F3048F16 Datasheet, PDF (171/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Bus Controller
φ
Address bus
CSn
AS
RD
Read
access
D₁₅ to D₈
D₇ to D ₀
HWR
Write
access
LWR
D₁₅ to D₈
D₇ to D ₀
Bus cycle
T₁
T₂
Odd external address in area n
High
Invalid
Valid
Undetermined data
Valid
Note: n = 7 to 0
Figure 6.10 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (2)
(Byte Access to Odd Address)
Rev. 3.00 Sep 27, 2006 page 143 of 872
REJ09B0325-0300