HD64F3048F16 Datasheet, PDF (567/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 14 Smart Card Interface
The receive margin can therefore be expressed as follows.
Receive margin in smart card mode:
M = 0.5 − ¹ − (L − 0.5) F − ^{D − 0.5} (1 + F) × 100%
2N
N
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 372)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L = 10)
F: Absolute deviation of clock frequency
From this equation, if F = 0 and D = 0.5 the receive margin is as follows.
D = 0.5, F = 0
M = {0.5 – 1/(2 × 372)} × 100%
= 49.866%
Retransmission
Retransmission is described below for the separate cases of transmit mode and receive mode.
• Retransmission when SCI is in Receive Mode (see figure 14.11)
(1) The SCI checks the received parity bit. If it detects an error, it automatically sets the PER
flag to 1. If the RIE bit in SCR is set to the enable state, an ERI interrupt is requested. The
PER flag should be cleared to 0 in SSR before the next parity bit sampling timing.
(2) The RDRF bit in SSR is not set to 1 for the error frame.
(3) If an error is not detected when the parity bit is checked, the PER flag is not set in SSR.
(4) If an error is not detected when the parity bit is checked, receiving operations are assumed
to have ended normally, and the RDRF bit is automatically set to 1 in SSR. If the RIE bit in
SCR is set to the enable state, an RXI interrupt is requested. If RXI is enabled as a DMA
transfer activation source, the RDR contents can be read automatically. When the DMAC
reads the RDR data, it automatically clears RDRF to 0.
(5) When a normal frame is received, at the error signal transmit timing, the data pin is held in
the high-impedance state.
Rev. 3.00 Sep 27, 2006 page 539 of 872
REJ09B0325-0300