HD64F3048F16 Datasheet, PDF (203/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Read cycle
Write cycle*
Section 7 Refresh Controller
Refresh cycle
φ
Address
bus
CS 3
(RAS)
HWR
(UCAS)
LWR
(LCAS)
RD
(WE)
RFSH
Row
Column
Row
Column
Area 3 top address
AS
Note: * 16-bit access
Figure 7.5(2) DRAM Control Signal Output Timing (2CAS Mode)
Refresh Cycle Priority Order
When there are simultaneous bus requests, the priority order is:
(High) External bus master > refresh controller > DMA controller > CPU
For details see section 6.3.7, Bus Arbiter Operation.
(Low)
Wait State Insertion
When bit AST3 is set to 1 in ASTCR, bus controller settings can cause wait states to be inserted
into bus cycles and refresh cycles. For details see section 6.3.5, Wait Modes.
Rev. 3.00 Sep 27, 2006 page 175 of 872
REJ09B0325-0300