HD64F3048F16 Datasheet, PDF (103/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 3 MCU Operating Modes
Bit 2—NMI Edge Select (NMIEG): Selects the valid edge of the NMI input.
Bit 2: NMIEG
0
1
Description
An interrupt is requested at the falling edge of NMI
An interrupt is requested at the rising edge of NMI
(Initial value)
Bit 1—Reserved: Read-only bit, always read as 1.
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized by the rising edge of the RES signal. It is not initialized in software standby mode.
Bit 0: RAME
0
1
Description
On-chip RAM is disabled
On-chip RAM is enabled
(Initial value)
3.4 Operating Mode Descriptions
3.4.1 Mode 1
Ports 1, 2, and 5 function as address pins A₁₉ to A₀, permitting access to a maximum 1-Mbyte
address space. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. If at least
one area is designated for 16-bit access in ABWCR, the bus mode switches to 16 bits.
3.4.2 Mode 2
Ports 1, 2, and 5 function as address pins A₁₉ to A₀, permitting access to a maximum 1-Mbyte
address space. The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. If all
areas are designated for 8-bit access in ABWCR, the bus mode switches to 8 bits.
3.4.3 Mode 3
Ports 1, 2, and 5 and part of port A function as address pins A₂₃ to A₀, permitting access to a
maximum 16-Mbyte address space. The initial bus mode after a reset is 8 bits, with 8-bit access to
all areas. If at least one area is designated for 16-bit access in ABWCR, the bus mode switches to
16 bits. A₂₃ to A₂₁ are valid when 0 is written in bits 7 to 5 of the bus release control register
(BRCR). (In this mode A₂₀ is always used for address output.)
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REJ09B0325-0300