HD64F3048F16 Datasheet, PDF (250/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 8 DMA Controller
8.4.2 I/O Mode
I/O mode can be selected independently for each channel.
One byte or word is transferred at each transfer request in I/O mode. A designated number of these
transfers are executed. One address is specified in the memory address register (MAR), the other
in the I/O address register (IOAR). The direction of transfer is determined automatically from the
activation source. The transfer is from the address specified in IOAR to the address specified in
MAR if activated by an SCI channel 0 receive-data-full interrupt, and from the address specified
in MAR to the address specified in IOAR otherwise.
Table 8.6 indicates the register functions in I/O mode.
Table 8.6 Register Functions in I/O Mode
Register
23
MAR
Function
Activated by
SCI0 Receive-
Data-Full
Interrupt
Other
Activation
0 ^Destination
address
register
Source
address
register
23
All 1s
15
7
0
IOAR
0
ETCR
Source
address
register
Transfer
counter
Destination
address
register
Transfer
counter
Legend:
MAR: Memory address register
IOAR: I/O address register
ETCR: Execute transfer count register
Initial Setting Operation
Destination or
source address
Incremented or
decremented
once per
transfer
Source or
destination
address
Held fixed
Number of
transfers
Decremented
once per
transfer until
H'0000 is
reached and
transfer ends
MAR and IOAR specify the source and destination addresses. MAR specifies a 24-bit source or
destination address, which is incremented or decremented as each byte or word is transferred.
IOAR specifies the lower 8 bits of a fixed address. The upper 16 bits are all 1s. IOAR is not
incremented or decremented.
Rev. 3.00 Sep 27, 2006 page 222 of 872
REJ09B0325-0300