HD64F3048F16 Datasheet, PDF (130/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 5 Interrupt Controller
5.2.3 IRQ Status Register (ISR)
ISR is an 8-bit readable/writable register that indicates the status of IRQ₀ to IRQ₅ interrupt
requests.
Bit
7

Initial value
0
Read/Write

6
5
4
3
2
1
0
 IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F
0
0
0
0
0
0
0
 R/(W)^* R/(W)^* R/(W)^* R/(W)^* R/(W)^* R/(W)^*
Reserved bits
Note: * Only 0 can be written, to clear flags.
IRQ ₅ to IRQ₀ flags
These bits indicate IRQ ₅ to IRQ₀
interrupt request status
ISR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 and 6—Reserved: Read-only bits, always read as 0.
Bits 5 to 0—IRQ₅ to IRQ₀ Flags (IRQ5F to IRQ0F): These bits indicate the status of IRQ₅ to
IRQ₀ interrupt requests.
Bits 5 to 0:
IRQ5F to IRQ0F
0
1
Note: n = 5 to 0
Description
[Clearing conditions]
(Initial value)
0 is written in IRQnF after reading the IRQnF flag when IRQnF = 1.
IRQnSC = 0, IRQn input is high, and interrupt exception handling is carried out.
IRQnSC = 1 and IRQn interrupt exception handling is carried out.
[Setting conditions]
IRQnSC = 0 and IRQn input is low.
IRQnSC = 1 and IRQn input changes from high to low.
Rev. 3.00 Sep 27, 2006 page 102 of 872
REJ09B0325-0300