HD64F3048F16 Datasheet, PDF (19/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

8.1.3 Functional Overview............................................................................................ 201
8.1.4 Input/Output Pins ................................................................................................. 203
8.1.5 Register Configuration......................................................................................... 203
8.2 Register Descriptions (Short Address Mode).................................................................... 205
8.2.1 Memory Address Registers (MAR) ..................................................................... 205
8.2.2 I/O Address Registers (IOAR) ............................................................................. 206
8.2.3 Execute Transfer Count Registers (ETCR).......................................................... 206
8.2.4 Data Transfer Control Registers (DTCR) ............................................................ 208
8.3 Register Descriptions (Full Address Mode)...................................................................... 211
8.3.1 Memory Address Registers (MAR) ..................................................................... 211
8.3.2 I/O Address Registers (IOAR) ............................................................................. 211
8.3.3 Execute Transfer Count Registers (ETCR).......................................................... 212
8.3.4 Data Transfer Control Registers (DTCR) ............................................................ 214
8.4 Operation .......................................................................................................................... 220
8.4.1 Overview.............................................................................................................. 220
8.4.2 I/O Mode.............................................................................................................. 222
8.4.3 Idle Mode............................................................................................................. 224
8.4.4 Repeat Mode ........................................................................................................ 227
8.4.5 Normal Mode....................................................................................................... 231
8.4.6 Block Transfer Mode ........................................................................................... 234
8.4.7 DMAC Activation................................................................................................ 239
8.4.8 DMAC Bus Cycle ................................................................................................ 241
8.4.9 DMAC Multiple-Channel Operation ................................................................... 247
8.4.10 External Bus Requests, Refresh Controller, and DMAC ..................................... 248
8.4.11 NMI Interrupts and DMAC.................................................................................. 249
8.4.12 Aborting a DMA Transfer ................................................................................... 250
8.4.13 Exiting Full Address Mode.................................................................................. 251
8.4.14 DMAC States in Reset State, Standby Modes, and Sleep Mode ......................... 252
8.5 Interrupts ........................................................................................................................... 253
8.6 Usage Notes ...................................................................................................................... 254
8.6.1 Note on Word Data Transfer................................................................................ 254
8.6.2 DMAC Self-Access ............................................................................................. 254
8.6.3 Longword Access to Memory Address Registers ................................................ 254
8.6.4 Note on Full Address Mode Setup ....................................................................... 254
8.6.5 Note on Activating DMAC by Internal Interrupts ............................................... 254
8.6.6 NMI Interrupts and Block Transfer Mode ........................................................... 256
8.6.7 Memory and I/O Address Register Values .......................................................... 256
8.6.8 Bus Cycle when Transfer Is Aborted ................................................................... 257
Section 9 I/O Ports .............................................................................................................. 259
9.1 Overview........................................................................................................................... 259
Rev. 3.00 Sep 27, 2006 page xvii of xxvi