HD64F3048F16 Datasheet, PDF (17/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

4.3 Interrupts ........................................................................................................................... 88
4.4 Trap Instruction................................................................................................................. 89
4.5 Stack Status after Exception Handling.............................................................................. 89
4.6 Notes on Stack Usage ....................................................................................................... 90
Section 5 Interrupt Controller .......................................................................................... 91
5.1 Overview........................................................................................................................... 91
5.1.1 Features................................................................................................................ 91
5.1.2 Block Diagram ..................................................................................................... 92
5.1.3 Pin Configuration................................................................................................. 93
5.1.4 Register Configuration......................................................................................... 93
5.2 Register Descriptions ........................................................................................................ 94
5.2.1 System Control Register (SYSCR) ...................................................................... 94
5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB)............................................. 95
5.2.3 IRQ Status Register (ISR).................................................................................... 102
5.2.4 IRQ Enable Register (IER) .................................................................................. 103
5.2.5 IRQ Sense Control Register (ISCR) .................................................................... 104
5.3 Interrupt Sources............................................................................................................... 105
5.3.1 External Interrupts ............................................................................................... 105
5.3.2 Internal Interrupts................................................................................................. 107
5.3.3 Interrupt Vector Table.......................................................................................... 107
5.4 Interrupt Operation............................................................................................................ 111
5.4.1 Interrupt Handling Process................................................................................... 111
5.4.2 Interrupt Sequence ............................................................................................... 116
5.4.3 Interrupt Response Time...................................................................................... 117
5.5 Usage Notes ...................................................................................................................... 118
5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction ...................... 118
5.5.2 Instructions That Inhibit Interrupts ...................................................................... 119
5.5.3 Interrupts during EEPMOV Instruction Execution.............................................. 119
5.5.4 Usage Notes on External Interrupts ..................................................................... 119
5.5.5 Notes on Non-Maskable Interrupts (NMI)........................................................... 121
Section 6 Bus Controller ................................................................................................... 123
6.1 Overview........................................................................................................................... 123
6.1.1 Features................................................................................................................ 123
6.1.2 Block Diagram ..................................................................................................... 124
6.1.3 Input/Output Pins ................................................................................................. 125
6.1.4 Register Configuration......................................................................................... 126
6.2 Register Descriptions ........................................................................................................ 126
6.2.1 Bus Width Control Register (ABWCR)............................................................... 126
6.2.2 Access State Control Register (ASTCR) ............................................................. 127
Rev. 3.00 Sep 27, 2006 page xv of xxvi