HD64F3048F16 Datasheet, PDF (367/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 10 16-Bit Integrated Timer Unit (ITU)
10.2.5 Timer Output Master Enable Register (TOER)
TOER is an 8-bit readable/writable register that enables or disables output settings for channels 3
and 4.
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0


EXB4 EXA4 EB3
EB4
EA4
EA3
1
1
1
1
1
1
1
1


R/W R/W R/W R/W R/W R/W
Reserved bits
Master enable TOCXA4, TOCXB4
These bits enable or disable output
settings for pins TOCXA₄ and TOCXB₄
Master enable TIOCA3, TIOCB3 , TIOCA4, TIOCB4
These bits enable or disable output settings for pins
TIOCA₃, TIOCB₃ , TIOCA₄, and TIOCB₄
TOER is initialized to H'FF by a reset and in standby mode.
Bits 7 and 6—Reserved: Read-only bits, always read as 1.
Bit 5—Master Enable TOCXB4 (EXB4): Enables or disables ITU output at pin TOCXB₄.
Bit 5: EXB4
0
1
Description
TOCXB₄ output is disabled regardless of TFCR settings (TOCXB₄ operates as
a generic input/output pin).
If XTGD = 0, EXB4 is cleared to 0 when input capture A occurs in channel 1.
TOCXB₄ is enabled for output according to TFCR settings
(Initial value)
Bit 4—Master Enable TOCXA4 (EXA4): Enables or disables ITU output at pin TOCXA₄.
Bit 4: EXA4
0
1
Description
TOCXA₄ output is disabled regardless of TFCR settings (TOCXA₄ operates as
a generic input/output pin).
If XTGD = 0, EXA4 is cleared to 0 when input capture A occurs in channel 1.
TOCXA₄ is enabled for output according to TFCR settings
(Initial value)
Rev. 3.00 Sep 27, 2006 page 339 of 872
REJ09B0325-0300