HD64F3048F16 Datasheet, PDF (640/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 18 ROM (H8/3048F-ONE: Single Power Supply, H8/3048B Mask ROM Version)
18.8.3 Error Protection
In error protection, an error is detected when H8/3048F-ONE runaway occurs during flash
memory programming/erasing*¹, or operation is not performed in accordance with the
program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase
operation prevents damage to the flash memory due to overprogramming or overerasing.
If the H8/3048F-ONE malfunctions during flash memory programming/erasing, the FLER bit is
set to 1 in FLMCR2 and the error protection state is entered. The FLMCR1, FLMCR2, EBR
settings*³ are retained, but program mode or erase mode is aborted at the point at which the error
occurred. Program mode or erase mode cannot be re-entered by re-setting the P, E bit. However,
PV, EV bit setting is enabled, and a transition can be made to verify mode*².
FLER bit setting conditions are as follows:
1. When the flash memory of the relevant address area is read during programming/erasing
(including vector read and instruction fetch)
2. Immediately after exception handling (excluding an illegal reset or trap instruction and
exception handling at zero division) during programming/erasing
3. When a SLEEP instruction (including software standby) is executed during
programming/erasing
4. When the CPU releases the bus to the DMAC, refresh controller, and external bus master
during programming/erasing
Error protection is released only by a reset (RES pin or WDT reset) and in hardware standby
mode.
Notes: 1. State in which the P bit or E bit in FLMCR1 is set to 1. Note that NMI input is disabled
in this state.
2. It is possible to perform a program-verify operation on the 128 bytes being
programmed, or an erase-verify on the block being erased.
3. FLMCR1 and EBR can be written to. However, the registers are initialized if a
transition is made to software standby mode while in the error-protected state.
Rev. 3.00 Sep 27, 2006 page 612 of 872
REJ09B0325-0300