HD64F3048F16 Datasheet, PDF (185/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Bus Controller
DDR Write Timing
Data
written
to
a
data
direction
register
(DDR)
to
change
a
CS
n
pin
from
CS
n
output
to
generic
input, or vice versa, takes effect starting from the T₃ state of the DDR write cycle. Figure 6.21
shows the timing when the CS₁ pin is changed from generic input to CS₁ output.
T₁
T₂
T₃
φ
Address
bus
P8DDR address
CS₁
High-impedance
Figure 6.21 DDR Write Timing
BRCR Write Timing
Data written to switch between A₂₃, A₂₂, or A₂₁ output and generic input or output takes effect
starting from the T₃ state of the BRCR write cycle. Figure 6.22 shows the timing when a pin is
changed from generic input to A₂₃, A₂₂, or A₂₁ output.
T₁
T₂
T₃
φ
Address
bus
A ₂₃ to A ₂₁
BRCR address
High-impedance
Figure 6.22 BRCR Write Timing
Rev. 3.00 Sep 27, 2006 page 157 of 872
REJ09B0325-0300