HD64F3048F16 Datasheet, PDF (678/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 20 Power-Down State
Clock
oscillator
RES
STBY
Oscillator
settling time
Reset
exception
handling
Figure 20.2 Hardware Standby Mode Timing
20.6 Module Standby Function
20.6.1 Module Standby Timing
The module standby function can halt several of the on-chip supporting modules (the ITU, SCI0,
SCI1, DMAC, refresh controller, and A/D converter) independently of the power-down state. This
standby function is controlled by bits MSTOP5 to MSTOP0 in MSTCR. When one of these bits is
set to 1, the corresponding on-chip supporting module is placed in standby and halts at the
beginning of the next bus cycle after the MSTCR write cycle.
20.6.2 Read/Write in Module Standby
When an on-chip supporting module is in module standby, read/write access to its registers is
disabled. Read access always results in H'FF data. Write access is ignored.
Rev. 3.00 Sep 27, 2006 page 650 of 872
REJ09B0325-0300