HD64F3048F16 Datasheet, PDF (854/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Appendix B Internal I/O Register
DACR—D/A Control Register
Bit
7
6
5
4
DAOE1 DAOE0 DAE

Initial value
0
0
0
1
Read/Write
R/W
R/W R/W

H'DE
3
2
1



1
1
1



D/A
0

1

D/A enable
Bit 7 Bit 6 Bit 5
DAOE1 DAOE0 DAE
0
0
1
0
1
1
0
0
1
1
Description
D/A conversion is disabled in channels 0 and 1
D/A conversion is enabled in channel 0
D/A conversion is disabled in channel 1
D/A conversion is enabled in channels 0 and 1
D/A conversion is disabled in channel 0
D/A conversion is enabled in channel 1
D/A conversion is enabled in channels 0 and 1
D/A conversion is enabled in channels 0 and 1
D/A output enable 0
0 DA₀ analog output is disabled
1 Channel-0 D/A conversion and DA₀ analog output are enabled
D/A output enable 1
0 DA₁ analog output is disabled
1 Channel-1 D/A conversion and DA₁ analog output are enabled
ADDRA H/L—A/D Data Register A H/L
H'E0, H'E1
A/D
Bit
Initial value
Read/Write
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0      
000000000000 0000
RRRRRRRRRRRR RRRR
ADDRAH
ADDRAL
A/D conversion data
10-bit data giving an
A/D conversion result
Rev. 3.00 Sep 27, 2006 page 826 of 872
REJ09B0325-0300