HD64F3048F16 Datasheet, PDF (362/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 10 16-Bit Integrated Timer Unit (ITU)
10.2.3 Timer Mode Register (TMDR)
TMDR is an 8-bit readable/writable register that selects PWM mode for channels 0 to 4. It also
selects phase counting mode and the overflow flag (OVF) setting conditions for channel 2.
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0

MDF FDIR PWM4 PWM3 PWM2 PWM1 PWM0
1
0
0
0
0
0
0
0

R/W R/W R/W R/W R/W R/W R/W
PWM mode 4 to 0
These bits select PWM
mode for channels 4 to 0
Flag direction
Selects the setting condition for the overflow
flag (OVF) in timer status register 2 (TSR2)
Phase counting mode flag
Selects phase counting mode for channel 2
Reserved bit
TMDR is initialized to H'80 by a reset and in standby mode.
Bit 7—Reserved: Read-only bit, always read as 1.
Bit 6—Phase Counting Mode Flag (MDF): Selects whether channel 2 operates normally or in
phase counting mode.
Bit 6: MDF
0
1
Description
Channel 2 operates normally
Channel 2 operates in phase counting mode
(Initial value)
Rev. 3.00 Sep 27, 2006 page 334 of 872
REJ09B0325-0300