HD64F3048F16 Datasheet, PDF (18/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

6.2.3 Wait Control Register (WCR).............................................................................. 128
6.2.4 Wait State Controller Enable Register (WCER) .................................................. 129
6.2.5 Bus Release Control Register (BRCR) ................................................................ 130
6.2.6 Chip Select Control Register (CSCR).................................................................. 132
6.3 Operation .......................................................................................................................... 133
6.3.1 Area Division ....................................................................................................... 133
6.3.2 Chip Select Signals .............................................................................................. 135
6.3.3 Data Bus............................................................................................................... 136
6.3.4 Bus Control Signal Timing .................................................................................. 137
6.3.5 Wait Modes.......................................................................................................... 145
6.3.6 Interconnections with Memory (Example) .......................................................... 151
6.3.7 Bus Arbiter Operation.......................................................................................... 153
6.4 Usage Notes ...................................................................................................................... 156
6.4.1 Connection to Dynamic RAM and Pseudo-Static RAM...................................... 156
6.4.2 Register Write Timing ......................................................................................... 156
6.4.3 BREQ Input Timing............................................................................................. 158
6.4.4 Transition To Software Standby Mode ................................................................ 158
Section 7 Refresh Controller ............................................................................................ 159
7.1 Overview........................................................................................................................... 159
7.1.1 Features................................................................................................................ 159
7.1.2 Block Diagram ..................................................................................................... 161
7.1.3 Input/Output Pins ................................................................................................. 162
7.1.4 Register Configuration......................................................................................... 162
7.2 Register Descriptions ........................................................................................................ 163
7.2.1 Refresh Control Register (RFSHCR)................................................................... 163
7.2.2 Refresh Timer Control/Status Register (RTMCSR) ............................................ 166
7.2.3 Refresh Timer Counter (RTCNT)........................................................................ 168
7.2.4 Refresh Time Constant Register (RTCOR) ......................................................... 168
7.3 Operation .......................................................................................................................... 169
7.3.1 Overview.............................................................................................................. 169
7.3.2 DRAM Refresh Control ....................................................................................... 171
7.3.3 Pseudo-Static RAM Refresh Control ................................................................... 185
7.3.4 Interval Timer ...................................................................................................... 190
7.4 Interrupt Source ................................................................................................................ 196
7.5 Usage Notes ...................................................................................................................... 196
Section 8 DMA Controller................................................................................................ 199
8.1 Overview........................................................................................................................... 199
8.1.1 Features................................................................................................................ 199
8.1.2 Block Diagram ..................................................................................................... 200
Rev. 3.00 Sep 27, 2006 page xvi of xxvi