HD64F3048F16 Datasheet, PDF (857/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

ADCR—A/D Control Register
Appendix B Internal I/O Register
H'E9
A/D
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
TRGE







0
1
1
1
1
1
1
1
R/W







Trigger enable
0 A/D conversion cannot be externally triggered
1 A/D conversion starts at the fall of the external trigger signal (ADTRG)
H8/3048F-ONE
H8/3048F
H8/3048B mask ROM version
H8/3048ZTAT
H8/3048 mask ROM version
H8/3047 mask ROM version
H8/3045 mask ROM version
H8/3044 mask ROM version
Not include this register
Include this register
ADCR—A/D Control Register
H'E9
A/D
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
TRGE







0
1
1
1
1
1
1
0
R/W






*
Trigger enable
0 A/D conversion cannot be externally triggered
1 A/D conversion starts at the fall of the external trigger signal (ADTRG)
Note: * Bit 0 must not be set to 1; in a write, 0 must always be written in this bit.
H8/3048F-ONE
H8/3048F
H8/3048B mask ROM version
H8/3048ZTAT
H8/3048 mask ROM version
H8/3047 mask ROM version
H8/3045 mask ROM version
H8/3044 mask ROM version
Include this register
Not include this register
Rev. 3.00 Sep 27, 2006 page 829 of 872
REJ09B0325-0300