HD64F3048F16 Datasheet, PDF (213/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 7 Refresh Controller
Set area 3 for 16-bit access
Set P8₁ DDR to 1 for CS₃ output
Set RTCOR
Set bits CKS2 to CKS0 in RTMCSR
Write H'3F in RFSHCR
Wait for DRAM to be initialized
DRAM can be accessed
Figure 7.14 Setup Procedure for Multiple 2CAS 4-Mbit DRAM Chips with 9-Bit Row
Address and 9-Bit Column Address (16-Mbyte Mode)
7.3.3 Pseudo-Static RAM Refresh Control
Refresh Request Interval and Refresh Cycle Execution
The refresh request interval is determined as in a DRAM interface, by the settings of RTCOR and
bits CKS2 to CKS0 in RTMCSR. The numbers of states required for pseudo-static RAM
read/write cycles and refresh cycles are the same as for DRAM (see table 7.4). The state
transitions are as shown in figure 7.3.
Rev. 3.00 Sep 27, 2006 page 185 of 872
REJ09B0325-0300