HD64F3048F16 Datasheet, PDF (396/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 10 16-Bit Integrated Timer Unit (ITU)
Example of Synchronization
Figure 10.27 shows an example of synchronization. Channels 0, 1, and 2 are synchronized, and are
set to operate in PWM mode. Channel 0 is set for counter clearing by compare match with GRB0.
Channels 1 and 2 are set for synchronous counter clearing. The timer counters in channels 0, 1,
and 2 are synchronously preset, and are synchronously cleared by compare match with GRB0. A
three-phase PWM waveform is output from pins TIOCA₀, TIOCA₁, and TIOCA₂. For further
information on PWM mode, see section 10.4.4, PWM Mode.
Value of TCNT0 to TCNT2 _{Cleared by compare match with GRB0}
GRB0
GRB1
GRA0
GRB2
GRA1
GRA2
H'0000
TIOCA₀
Time
TIOCA₁
TIOCA₂
Figure 10.27 Synchronization (Example)
Rev. 3.00 Sep 27, 2006 page 368 of 872
REJ09B0325-0300