HD64F3048F16 Datasheet, PDF (557/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 14 Smart Card Interface
The following equation calculates the bit rate register (BRR) setting from the system clock
frequency and bit rate. N is an integer from 0 to 255, specifying the value with the smaller error.
φ
N = _{1488 × 22n−1 × B}
× 10⁶ − 1
Table 14.6 BRR Settings for Typical Bit Rate (bits/s) (when n = 0)
φ (MHz)
7.1424 10.00 10.7136 13.00 14.2848 16.00
18.00
20.00
25.00
Bit/s N Error N Error N Error N Error N Error N Error N Error N Error N Error
9600 0 0.00 1 30.00 1 25.00 1 8.99 1 0.00 1 12.01 2 15.99 2 6.66 3 12.49
Table 14.7 Maximum Bit Rates for Various Frequencies (Smart Card Interface)
φ (MHz)
Maximum Bit Rate (bits/s)
N
n
7.1424
9600
0
0
10.00
13441
0
0
10.7136
14400
0
0
13.00
17473
0
0
14.2848
19200
0
0
16.00
21505
0
0
18.00
24194
0
0
20.00
26882
0
0
25.00
33602
0
0
The bit rate error is calculated from the following equation.
Error (%) =
φ
1488 × 2^2n−1 × B × (N + 1)
× 10⁶ − 1
× 100
Rev. 3.00 Sep 27, 2006 page 529 of 872
REJ09B0325-0300