HD64F3048F16 Datasheet, PDF (378/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 10 16-Bit Integrated Timer Unit (ITU)
10.2.12 Timer Status Register (TSR)
TSR is an 8-bit register. The ITU has five TSRs, one in each channel.
Channel
0
1
2
3
4
Abbreviation
TSR0
TSR1
TSR2
TSR3
TSR4
Function
Indicates input capture, compare match, and overflow status
Bit
7

Initial value
1
Read/Write

6
5


1
1


4
3
2
1
0


OVF IMFB IMFA
1
1
0
0
0

 R/(W)* R/(W)* R/(W)*
Reserved bits
Overflow flag
Status flag indicating
overflow or underflow
Input capture/compare match flag B
Status flag indicating GRB compare
match or input capture
Input capture/compare match flag A
Status flag indicating GRA compare
match or input capture
Note: * Only 0 can be written, to clear the flag.
Each TSR is an 8-bit readable/writable register containing flags that indicate TCNT overflow or
underflow and GRA or GRB compare match or input capture. These flags are interrupt sources
and generate CPU interrupts if enabled by corresponding bits in TIER.
TSR is initialized to H'F8 by a reset and in standby mode.
Bits 7 to 3—Reserved: Read-only bits, always read as 1.
Rev. 3.00 Sep 27, 2006 page 350 of 872
REJ09B0325-0300