HD64F3048F16 Datasheet, PDF (583/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Table 15.4 A/D Conversion Time (Single Mode)
CKS = 0
Symbol Min Typ Max
Synchronization delay
t_D
10
—
17
Input sampling time
t_SPL
—
63
—
A/D conversion time
t_CONV
259 —
266
Note: Values in the table are numbers of states.
Section 15 A/D Converter
CKS = 1
Min Typ Max
6
—
9
—
31
—
131 —
134
15.4.4 External Trigger Input Timing
A/D conversion can be externally triggered. When the TRGE bit is set to 1 in ADCR, external
trigger input is enabled at the ADTRG pin. A high-to-low transition at the ADTRG pin sets the
ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan
modes, are the same as if the ADST bit had been set to 1 by software. Figure 15.6 shows the
timing.
φ
ADTRG
Internal trigger
signal
ADST
A/D conversion
Figure 15.6 External Trigger Input Timing
Rev. 3.00 Sep 27, 2006 page 555 of 872
REJ09B0325-0300