HD64F3048F16 Datasheet, PDF (380/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 10 16-Bit Integrated Timer Unit (ITU)
10.2.13 Timer Interrupt Enable Register (TIER)
TIER is an 8-bit register. The ITU has five TIERs, one in each channel.
Channel
0
1
2
3
4
Abbreviation
TIER0
TIER1
TIER2
TIER3
TIER4
Function
Enables or disables interrupt requests.
Bit
7
6
5
4
3
2
1
0





OVIE IMIEB IMIEA
Initial value
1
1
1
1
1
0
0
0
Read/Write





R/W R/W R/W
Reserved bits
Overflow interrupt enable
Enables or disables OVF
interrupts
Input capture/compare match
interrupt enable B
Enables or disables IMFB interrupts
Input capture/compare match
interrupt enable A
Enables or disables IMFA
interrupts
Each TIER is an 8-bit readable/writable register that enables and disables overflow interrupt
requests and general register compare match and input capture interrupt requests.
TIER is initialized to H'F8 by a reset and in standby mode.
Bits 7 to 3—Reserved: Read-only bits, always read as 1.
Rev. 3.00 Sep 27, 2006 page 352 of 872
REJ09B0325-0300