HD64F3048F16 Datasheet, PDF (790/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Appendix B Internal I/O Register
DTCR0B—Data Transfer Control Register 0B (cont)
H'2F
DMAC0
• Full address mode
Bit
7
6
5
4
3
2
1
0
DTME

DAID DAIDE TMS DTS2B DTS1B DTS0B
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W R/W
R/W
R/W R/W
Data transfer select 2B to 0B
Bit 2 Bit 1 Bit 0
Data Transfer Activation Source
DTS2B DTS1B DTS0B Normal Mode
Block Transfer Mode
0
0
0 Auto-request
(burst mode)
Compare match/input capture
A from ITU channel 0
1 Not available
Compare match/input capture
A from ITU channel 1
1
0 Auto-request
(cycle-steal mode)
Compare match/input capture
A from ITU channel 2
1 Not available
Compare match/input capture
A from ITU channel 3
1
0
0 Not available
Not available
1 Not available
Not available
1
0 Falling edge of DREQ Falling edge of DREQ
1 Low level input at DREQ Not available
Transfer mode select
0 Destination is the block area in block transfer mode
1 Source is the block area in block transfer mode
Destination address increment/decrement (bit 5)
Destination address increment/decrement enable (bit 4)
Bit 5 Bit 4
DAID DAIDE Increment/Decrement Enable
0
0 MARB is held fixed
1 Incremented: If DTSZ = 0, MARB is incremented by 1 after each transfer
If DTSZ = 1, MARB is incremented by 2 after each transfer
1
0 MARB is held fixed
1 Decremented: If DTSZ = 0, MARB is decremented by 1 after each transfer
If DTSZ = 1, MARB is decremented by 2 after each transfer
Data transfer master enable
0 Data transfer is disabled
1 Data transfer is enabled
Rev. 3.00 Sep 27, 2006 page 762 of 872
REJ09B0325-0300