HD64F3048F16 Datasheet, PDF (663/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 19 Clock Pulse Generator
Table 19.4(2) Clock Timing for H8/3048B Group (2 MHz ≤ f < 8 MHz)
V_CC =
3.0 V to 3.6 V
V_CC =
5.0 V ±10%
Item
Symbol Min Max
Min Max
External clock
t
EXL
input low pulse
width
57
—
57
—
External clock
t_EXH
input high pulse
width
57
—
57
—
External clock
t_EXr
rise time
—
5
—
5
External clock
t_EXf
fall time
—
5
—
5
Clock low pulse t_CL
width
0.4
0.6
80
—
0.4
0.6
80
—
Clock high pulse
width
External clock
output settling
delay time
t_CH
t_DEXT^*
0.4
0.6
80
—
500 —
0.4
0.6
80
—
500 —
Note: * t_DEXT includes a RES pulse width (t_RESW). t_RESW = 20 t_cyc
Unit Test Conditions
ns Figure 19.6
ns
ns
ns
t_cyc
φ ≥ 5 MHz Figure
ns φ < 5 MHz ^21.7
t_cyc
φ ≥ 5 MHz
ns φ < 5 MHz
µs Figure 19.7
EXTAL
t_EXH
t_EXL
V_CC × 0.7
0.3 V
t_EXr
t_EXf
Figure 19.6 External Clock Input Timing
V_CC × 0.5
Rev. 3.00 Sep 27, 2006 page 635 of 872
REJ09B0325-0300