HD64F3048F16 Datasheet, PDF (416/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 10 16-Bit Integrated Timer Unit (ITU)
Sample Buffering Setup Procedure
Figure 10.48 shows a sample buffering setup procedure.
Buffering
Select general register functions 1 1. Set TIOR to select the output compare or input
capture function of the general registers.
2. Set bits BFA3, BFA4, BFB3, and BFB4 in TFCR
Set buffer bits
2
to select buffering of the required general registers.
3. Set the STR bits to 1 in TSTR to start the timer
counters.
Start counters
3
Buffered operation
Figure 10.48 Buffering Setup Procedure (Example)
Examples of Buffering
Figure 10.49 shows an example in which GRA is set to function as an output compare register
buffered by BRA, TCNT is set to operate as a periodic counter cleared by GRB compare match,
and TIOCA and TIOCB are set to toggle at compare match A and B. Because of the buffer setting,
when TIOCA toggles at compare match A, the BRA value is simultaneously transferred to GRA.
This operation is repeated each time compare match A occurs. Figure 10.50 shows the transfer
timing.
Rev. 3.00 Sep 27, 2006 page 388 of 872
REJ09B0325-0300