HD64F3048F16 Datasheet, PDF (233/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 8 DMA Controller
8.2 Register Descriptions (Short Address Mode)
In short address mode, transfers can be carried out independently on channels A and B. Short
address mode is selected by bits DTS2A and DTS1A in data transfer control register A (DTCRA)
as indicated in table 8.4.
Table 8.4 Selection of Short and Full Address Modes
Channel
0
Bit 2:
DTS2A
1
Bit 1:
DTS1A
1
Other than above
1
1
1
Other than above
Description
DMAC channel 0 operates as one channel in full address
mode
DMAC channels 0A and 0B operate as two independent
channels in short address mode
DMAC channel 1 operates as one channel in full address
mode
DMAC channels 1A and 1B operate as two independent
channels in short address mode
8.2.1 Memory Address Registers (MAR)
A memory address register (MAR) is a 32-bit readable/writable register that specifies a source or
destination address. The transfer direction is determined automatically from the activation source.
An MAR consists of four 8-bit registers designated MARR, MARE, MARH, and MARL. All bits
of MARR are reserved: they cannot be modified and are always read as 1.
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value 1 1 1 1 1 1 1 1
Undetermined
Read/Write         R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MARR
MARE
MARH
MARL
Source or destination address
An MAR functions as a source or destination address register depending on how the DMAC is
activated: as a destination address register if activation is by a receive-data-full interrupt from the
serial communication interface (SCI) (channel 0), and as a source address register otherwise.
Rev. 3.00 Sep 27, 2006 page 205 of 872
REJ09B0325-0300