HD64F3048F16 Datasheet, PDF (471/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

12.1.4 Register Configuration
Table 12.2 summarizes the WDT registers.
Table 12.2 WDT Registers
Address^*1
Write^*2 Read
Name
H'FFA8 H'FFA8 Timer control/status register
H'FFA9 Timer counter
H'FFAA H'FFAB Reset control/status register
Notes: 1. Lower 16 bits of the address.
2. Write word data starting at this address.
3. Only 0 can be written in bit 7, to clear the flag.
Section 12 Watchdog Timer
Abbre-
viation
TCSR
TCNT
RSTCSR
R/W
R/(W)^*3
R/W
R/(W)^*3
Initial
Value
H'18
H'00
H'3F
12.2 Register Descriptions
12.2.1 Timer Counter (TCNT)
TCNT is an 8-bit readable and writable* up-counter.
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from an internal
clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from
H'FF to H'00), the OVF bit is set to 1 in TCSR. TCNT is initialized to H'00 by a reset and when
the TME bit is cleared to 0.
Note: * TCNT is write-protected by a password. For details see section 12.2.4, Notes on
Register Rewriting.
Rev. 3.00 Sep 27, 2006 page 443 of 872
REJ09B0325-0300