HD64F3048F16 Datasheet, PDF (618/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 18 ROM (H8/3048F-ONE: Single Power Supply, H8/3048B Mask ROM Version)
Table 18.4 Flash Memory Erase Blocks
Block (Size)
EB0 (1 kbyte)
EB1 (1 kbyte)
EB2 (1 kbyte)
EB3 (1 kbyte)
EB4 (28 kbytes)
EB5 (32 kbytes)
EB6 (32 kbytes)
EB7 (32 kbytes)
Address
H'000000–H'0003FF
H'000400–H'0007FF
H'000800–H'000BFF
H'000C00–H'000FFF
H'001000–H'007FFF
H'008000–H'00FFFF
H'010000–H'017FFF
H'018000–H'01FFFF
18.5.4 RAM Control Register (RAMCR)
Bit
7
6
5
4
3
2
1
0



 RAMS RAM2 RAM1 
Modes ^{Initial value}
1
1
1
1
0
0
0
0
1 to 4 Read/Write




R
R
R

Modes ^{Initial value}
1
1
1
1
0
0
0
0
5 to 7 _Read/Write




R/W
R/W
R/W
R/W
Reserved bits
Reserved bit
RAM2, RAM1
Used together with bit 3 to select
a flash memory area
RAM select
Used together with bits 2 and 1 to select
a flash memory area
RAMCR selects the RAM area to be used when emulating real-time flash memory programming.
RAMCR initialized to H'F0 by a reset and in hardware standby mode. It is not initialized in
software standby mode. RAMCR settings should be made in user mode or user program mode.*
Note: * When performing flash memory emulation by RAM, the RAME bit in SYSCR must be
set to 1.
RAM area settings are shown in table 18.5. To ensure correct operation of the emulation function,
the ROM for which RAM emulation is performed should not be accessed immediately after this
Rev. 3.00 Sep 27, 2006 page 590 of 872
REJ09B0325-0300