HD64F3048F16 Datasheet, PDF (415/903 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 10 16-Bit Integrated Timer Unit (ITU)
10.4.8 Buffering
Buffering operates differently depending on whether a general register is an output compare
register or an input capture register, with further differences in reset-synchronized PWM mode and
complementary PWM mode. Buffering is available only in channels 3 and 4. Buffering operations
under the conditions mentioned above are described next.
• General register used for output compare
The buffer register value is transferred to the general register at compare match.
See figure 10.46.
Compare match signal
BR
GR
Comparator
TCNT
Figure 10.46 Compare Match Buffering
• General register used for input capture
The TCNT value is transferred to the general register at input capture. The previous general
register value is transferred to the buffer register.
See figure 10.47.
Input capture signal
BR
GR
TCNT
Figure 10.47 Input Capture Buffering
• Complementary PWM mode
The buffer register value is transferred to the general register when TCNT3 and TCNT4
change counting direction. This occurs at the following two times:
 When TCNT3 compare matches GRA3
 When TCNT4 underflows
• Reset-synchronized PWM mode
The buffer register value is transferred to the general register at compare match A3.
Rev. 3.00 Sep 27, 2006 page 387 of 872
REJ09B0325-0300